SG2000 is a high-performance, low-power chip for edge surveillance cameras, facial recognition machines, and smart home devices. It features H.264/H.265 video compression, ISP capabilities, and supports HDR, 3D noise reduction, defogging, and lens correction for professional-grade video quality.
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- BlockDiagram
- Оборудование
- Applications
- Documents
- DesignResources
- ChoosingUs
SG2000 is a high-performance, low-power chip designed for various product fields such as edge intelligent surveillance IP cameras, local facial recognition attendance machines, and smart home devices. It integrates H.264/H.265 video compression and decoding and ISP capabilities. It supports various image enhancement and correction algorithms like HDR wide dynamic range, 3D noise reduction, defogging, and lens distortion correction, providing customers with professional-grade video image quality.
The chip also integrates an in-house TPU, delivering approximately 0.5TOPS of computing power under INT8 operations. The specially designed TPU scheduling engine efficiently provides high-bandwidth data flow for tensor processing unit cores. It also offers users a powerful deep learning model compiler and software SDK development kit. Mainstream deep learning frameworks such as Caffe, Pytorch, ONNX, MXNet, and TensorFlow (Lite) can be easily ported to this platform.
BlockDiagram
Оборудование
RISC-V CPU
- 1 x C906@1GHz + 1 x C906@700MHz
Arm CPU
- 1 x Cortex-A53@1GHz
MCU
- 8051@6KB SRAM
NPU
- 0.5 TOPS@INT8
Memory
- Sip DRAM 512M
Video Module
- ISP 5M@30fps
- 2L MIPI DSI 5M@30fps
- 4L or 2L+2L MIPI CSI 5M@30fps
- H.265/H.264 Decoding and Encoding 5M@30fps
Audio Module
- 16bit Audio Codec
- 2 x I2S/PCM
- 1 x DMIC
Storage
- SPI-NOR, SPI-NAND, eMMC5.0, 2 x SDIO3.0
Network
- 10M/100M MAC PHY
Security Module
- Crypto/Secure boot/TRNG/Efuze
Peripherals
- 1 x USB2.0 DRD/5 x UART/4 x SPI/16 x PWM/1 x IR/6 x I2C/6 x ADC/ GPIOs
Temperature Range
- 0℃~70℃
Package Type
- LFBGA
Package Dimensions
- 10mm x 10mm x 1.3mm
Pin Pitch
- 0.65mm
Total Pins
- 205
Applications
Intelligent door locks
Video Conference
Industrial Internet of Things
intelligent transport
Documents
SelectionMethod
Hardware Design
- SG2000-BGA-SIP-V11-16.2
DSN Jun 5,2023 1.94 MB
- SG2000-BGA-SIP-V11
PDF Jun 5,2023 1.37 MB
- SG2000-WEVB-0007A-V04-SCH
PDF Jun 5,2023 1.07 MB
- WDMB-0007B-V02-Component-Placement-Diagram
PDF Jun 5,2023 2.3 MB
- WDMB-0007B-V02
BRD Jun 5,2023 4.61 MB
- WDMB-0007B-V02
PCB Jun 5,2023 3.77 MB
- SG2000-Hardware-PCB-Layout-Guide
PDF Jun 5,2023 10.9 MB
- SG2000-PINOUT
XLSX Jun 5,2023 3.86 MB
- duo_s_SCH_v1.1.pdf
PDF Jun 2,2024 399 KB
DesignResources
SelectionMethod
Development Hardware
The Milk-V Duo S is an upgraded version of the Duo, utilizing an upgraded SG2000 host controller with larger 512MB of RAM and expanded IO functions. Optional eMMC and WI-FI/BT, support switching ARM/RISC-V boot.
The Huashan Sect - CV181 Series Development Board, jointly released by Aligned Computing and Eco-Partner Hardware for a hundred thousand reasons, is an open-source ecosystem development board providing a RISC-V-based open development environment for extensive users. It focuses on visual and AI scene development, aiming to grow together with a vast community of developers.
ChoosingUs
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We have mature PCBA solutions and extensive product design experience, offering customized solutions tailored to your unique needs.
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