SOPHON SG2042

Introduction of SOPHON SG2042

The SG2042 server chip is based on the RISC-V instruction set architecture (ISA) and features a 64-core server-grade chip designed to meet high-performance computing needs. It offers scalability, flexibility, and customization, with integrated circuits including high-speed cache (L3Cache 64MB), memory controller (4 DDR4-3200), network interface, and PCI Express® controller (x32 PCI Express Gen4.0), supporting general-purpose operating systems such as Linux®. The SG2042 has a clock speed of 2GHz and a design consisting of 16 clusters, each containing 4 RISC-V cores, with each core featuring L1-D 64KB and L1-I 64KB. Each cluster shares a design of L2 1MB. The L3 System cache has a capacity of 64MB. The SG2042 supports interconnect between two chips via CCIX and has 4 DDR4-3200 controllers, supporting RDIMM, ECC, and UDIMM. The chip also has 32x PCI E Gen4.0 interfaces, integrated eMMC5.1, SDIO 3.0, SPI x2, I2C x4, UART x4, and gigabit Ethernet MAC.

SG2042 TRM

We have open sourced the TRM of SOPHON SG2042 to GitHub. please check it out.